1. Field of the Invention
This invention relates generally to a magnetoresistive random access memory (MRAM) cell formed in a magnetic tunneling junction (MTJ) configuration and particularly to a method of improving its coupling to an adjacent bit line.
2. Description of the Related Art
The magnetic tunneling junction (MTJ) device is a form of giant magnetoresistive (GMR) device in which the relative orientation of the magnetic moments of parallel, vertically separated, upper and lower magnetized layers controls the flow of spin-polarized electrons tunneling through a very thin dielectric layer (the tunneling barrier layer) formed between those layers. When injected electrons pass through the upper layer they are spin polarized by interaction with the magnetic moment of that layer. The probability of such an electron then tunneling through the intervening tunneling barrier layer into the lower layer then depends on the availability of states within the lower electrode that the tunneling electron can occupy. This number, in turn, depends on the magnetization direction of the lower electrode. The tunneling probability is thereby spin dependent and the magnitude of the current (tunneling probability times number of electrons impinging on the barrier layer) depends upon the relative orientation of the magnetizations of magnetic layers above and below the barrier layer. The MTJ device can therefore be viewed as a kind of variable resistor, since different relative orientations of the magnetic moments will change the magnitude of a current passing through the device.
FIG. 1 is a schematic cross-sectional view of a typical MTJ layer structure (10) (hereinafter referred to as an MTJ element) formed in what is called a spin-filter configuration. In this particular form, the lower one of the two magnetized layers, now called a pinned layer, has the direction of its magnetic moment fixed in direction, while the magnetic moment of the upper or free layer remains free to move in response to external stimuli. Looking from the bottom up, the layer configuration includes a seed layer (5), that is used as a foundation on which to form successive overlayers. A layer of antiferromagnetic material, the AFM layer (15), is formed on the seed layer and will be used to pin the magnetic moment of the pinned layer by a form of magnetic coupling called exchange coupling. The lower, pinned layer (20) is a layer of ferromagnetic material formed on the AFM layer, or it can be a pair of ferromagnetic layers separated by a non-magnetic coupling layer. The tunneling barrier layer or junction layer (30) is then formed on the pinned layer, typically by first forming a layer of a metal such as aluminum (or magnesium) and then subjecting the metal to oxidation. The free layer (40) is a ferromagnetic layer that is then formed on the junction layer. Finally, a protective capping layer (50) is formed on the free layer. As will be discussed below, the capping layer, which is typically a layer of Ta, TaN, Ti or TiN, plays an important role when the MTJ devices are planarized to render their upper surfaces co-planar with surrounding insulation.
After the layers are formed, the device is subjected to external magnetic fields at various temperatures to produce the magnetic moments in the pinned and free layers. If the pinned layer is formed as a coupled pair of ferromagnetic layers, the annealing process can be used to produce antiparallel magnetic moments so that the pinned layer has a substantially zero total magnetic moment.
If the magnetization of the free layer is allowed to move continuously, as when it is acted on by a continuously varying external magnetic field, the MTJ device can be used as a read-head for sensing magnetic field variations produced by moving magnetically recorded media. If the magnetization of the free layer is constrained to move in only two directions, eg. parallel to or antiparallel to the magnetization of the pinned layer, then the MTJ device can be used as a memory device, called a magnetic random access memory device or MRAM. When used as an MRAM, the MTJ device provides only two resistance values, maximum resistance in the antiparallel orientations of the free and pinned layer magnetizations and minimum resistance in their parallel orientation. Thus, when the device is in one of its two resistance states it can be said to store a logical zero or one. By sensing the resistance state, the device is “read,” and by changing the resistance state, the device is written upon. The writing of such a device is accomplished by its interaction with the magnetic fields of current carrying lines, called word lines and bit lines, that are vertically separated and typically pass above or below the MTJ device in mutually perpendicular directions.
FIG. 2 is a schematic cross-sectional view of two prior art MTJ devices and their associated word and bit lines. The devices (10) and (11) are not shown in their layered detail, but it can be assumed they are identical to the device in FIG. 1. On the bottom surface of each device there is an electrode (20) and (21), that is used to sense the resistance state of each device. A bit line (30) contacts the upper surface of each device and runs from left to right in the plane of the figure. A layer of insulation (60) surrounds the devices and also vertically separates the bit line (30) from the word lines, (70) and (71), that pass over the devices and are directed perpendicularly to the plane of the figure. The word lines are also separated from each other by layers of insulation (63). It is understood by those skilled in the art that these layers of insulation may be deposited prior to the formation of the word and bit lines and then the word and bit lines may be plated within channels or trenches formed in the insulation. Once the word and bit lines are formed as shown in this figure, the passage of currents through them will produce magnetic fields that change the direction of the magnetic moment of the free layer within the MTJ devices. While in FIG. 2 word lines are shown above the MTJ elements, in some other configurations word lines are formed beneath the MTJ elements. In some configurations bit lines do not touch the upper surfaces of the MTJ elements and separate top electrodes are used for the reading operation.
To make dense arrays of MTJ devices and their associated word and bit lines, it is desirable to have a uniformly flat and co-planar topography in which the upper surfaces of the MTJ devices are exposed for making electrical contact and are co-planar with the insulation layers that are formed about them. The co-planarity of these layers is generally achieved by use of chemical mechanical polishing (CMP) processes. Maintaining co-planarity of the device contact surfaces is of great importance because it will ensure that the distance from the bit lines to the free layers of all the devices is uniform, thereby also ensuring that currents in the bit lines will produce the same write fields at the free layers of each device. In addition, uniform smoothness of the insulation layers and their co-planarity with the exposed device surfaces will also eliminate leakage problems between the bit lines and the MTJ device. Unfortunately, prior art methods using CMP do not achieve the uniformity and co-planarity that is so desirable.
Referring now to FIGS. 3a-3c, there is shown a sequence of prior art processing steps that are typically used to render the upper surfaces of an array of MTJ devices co-planar with each other and with the surrounding insulation. For simplicity and attention to detail, the figures show only the process as applied to a single MTJ device, but the presence of an array of adjacent devices can be imagined.
Looking first at FIG. 3a, there is shown a cross-sectional side view of a patterned MTJ device (10) already formed on a bottom electrode (20). The tunneling barrier layer (30), the free layer (40) and the capping layer (50) are indicated for reference. It can be assumed that the MTJ device has been patterned as shown above to produce a final lateral width, W, by applying either an IBE (ion beam etch) or RIE (reactive ion etch) through a mask to remove unwanted side portions and that the mask has already been stripped away. It is well known in the art that IBE and RIE belong to a class of anisotropic etching processes, meaning that they etch preferentially in one direction (the vertical direction herein) rather than in the other direction (the horizontal direction herein). In the following process steps, such etches will be used and referred to specifically.
Referring now to FIG. 3b, there is shown the fabrication of FIG. 3a now including the additional formation of deposited layer of insulation (70), such as a layer of SiO2, to cover all exposed surfaces of the MTJ device (10) as well as the upper surfaces of the bottom electrode (20).
Referring finally to FIG. 3c, there is shown the fabrication of FIG. 3b subsequent to a CMP process to remove insulation (70) from the upper surface of the device and surrounding regions and form what is intended to be a substantially smooth co-planar upper surface. As is shown schematically in the figure, however, the typical effects of such a CMP process is to remove so much of the insulation on either side of the MTJ device, that the upper insulation surface (75) is recessed relative to the exposed capping layer (50), which is also thinned. The degree of recession varies from device to device ranging to 400 angstroms and above. If the surrounding insulation material falls below the level of the barrier layer (30), the device will short out electrically due to current leakage between the layers below the barrier layer to the electrical lines subsequently formed above the device (and not shown here). Clearly, since the operation of an MTJ device depends on electron tunneling through the barrier layer, any direct leakage from the lateral side surfaces of the device to surrounding current-carrying lines would severely and adversely affect the device performance.
Other approaches have been tried, particularly approaches that involve forming additional capping layers over the patterned MTJ device before the final layer of insulation is applied. Although these approaches seem to have the advantage of providing an accurate spacing between the bit line and the free layer, they do not eliminate shorting from the sides of the MTJ device (see below) and, therefore, do not have the advantages of the present invention.
A particular prior art approach to the present problem uses silicon nitride (SiNx) layers to furnish additional protection. This approach is briefly summarized and illustrated very schematically in FIGS. 4a-4e. The method begins with the structure of FIG. 3a, a patterned MTJ device (10) formed on a bottom electrode (20). The MTJ device includes a tunneling barrier layer (30), a free layer (40) and a capping layer (50).
Referring next to FIG. 4a, there is shown, schematically, the fabrication of FIG. 3a, now including the formation of a thin layer (90) of silicon nitride (SiNx) conformally covering the MTJ device (10) and the upper surfaces of the bottom electrode (20).
Referring next to FIG. 4b, there is shown, schematically, the fabrication of FIG. 4a wherein an anisotropic etching process, such as an IBE or RIE, has removed portions of the nitride layer laterally extending on the bottom electrode (20) beyond the MTJ device, leaving sidewalls (95) on both lateral side surfaces of the MTJ device
Referring now to FIG. 4c, there is shown, schematically, the fabrication of FIG. 4b wherein a layer of insulation (70), such as a layer of SiO2, is now formed conformally covering the upper capping layer (50) of the MTJ device, the sidewall (95) SiNx layers on the MTJ device as well as the surrounding lower electrode (20) surfaces. It is at this point that a CMP process is applied to remove excess insulation from the top of the MTJ device and the surrounding regions.
Referring now to FIG. 4d, there is seen a schematic drawing of the results of a CMP process to produce the desired smooth, planar upper surface in which the upper surface of the MTJ device is rendered substantially co-planar with the upper surface of the surrounding insulating material (70). As is shown in the figure, the CMP process is stopped by the sidewalls (95) and the MTJ capping layer (50) of Ta, Ti, TaN or TiN. The sidewalls (95) prevent exposure of the sides of the MTJ device even if the CMP process recesses the surface of the insulation layer (70) below the upper surface of the MTJ device.
Referring to FIG. 4e there is shown a subsequent process step that is preparatory to the formation of a conducting bit line (or other conducting electrode) over the top of the structure of FIG. 4d. Typically, the bit line is manufactured using a Cu damascene process in which a copper line is formed in a lined trench. To prepare for this, a layer of SiNx (100) is first deposited, followed by a thicker layer of SiO2 (110). Trenches are then etched into these two layers and a layer of Cu, surrounded by adhesion/barrier layers (neither being shown) are formed in the trenches. During the etching of the SiNx layer (100) the SiNx sidewall layers (95) are also etched, leading to the disadvantageous formation shown in FIG. 4f. 
Referring to FIG. 4f, there is shown the fabrication of FIG. 4e, wherein an etching of the SiO2 (110) and SiNx (100) layers has also caused an etching and partial removal of the protective sidewall spacers (95) previously formed on the MTJ structure. The removal of the portions of the sidewall exposes the sides of the MTJ device to possible shorting, which the sidewall is originally meant to prevent.
Another approach is taught in related patent application HMG 05-012/016 and is fully incorporated herein by reference. In that process a SiNx capping layer is used to stop the CMP process.
Referring to FIG. 5a there is shown an MTJ device (10) identical to that in FIG. 3a. In FIG. 5b, the MTJ device of FIG. 5a is shown subsequent to the formation of a SiNx layer (120) conformally covering all exposed surfaces of the MTJ device as well as the bottom electrode (20) on which it is formed. Referring next to FIG. 5c, there is shown the fabrication of FIG. 5b subsequent to the formation of a layer of SiO2 (125) to conformally cover the layer of SiNx (120).
Referring next to FIG. 5d, there is shown the fabrication of FIG. 5c subsequent to the application of a CMP process to remove SiO2 material from the layer (125) on top of the device and stop at the SiNx layer (120). Because CMP removes SiNx at a slower rate than SiO2, the SiNx layer will exhibit little or no recession of its surface (121), although the surrounding surface of the SiO2 layer (126) may be recessed below the surface of the SiNx. Finally, referring to FIG. 5e, there is shown the removal of the SiNx layer (120) from the capping layer (50) by an IBE or RIE etching process, leaving the sidewall portion of the SiNx layer relatively intact. A top electrode can now be deposited directly on the capping layer of the MTJ device.
It is to be noted that the removal of the SiNx layer by an IBE or RIE, is a much more selective and controllable removal process than the CMP process. The basic idea in the method just described is to remove with great precision all of the SiNx spacer layer from over the Ta capping layer, thereby leaving the capping layer substantially unthinned from its original carefully controlled, as-deposited thickness. This method assures a uniform spacing between the upper bit line and the free layer, because it is only the capping layer that separates the one from the other. Unfortunately, as was seen in FIG. 4e, when the top electrode is to be formed by a Cu damascene process, the device is completely covered by additional SiNx and SiO2 layers which must be etched. This etching will partially remove the desirable sidewalls protecting the MTJ device. Thus, even though the problem of uniform spacing between the bit line and the free layer is largely eliminated, the problem of shorting from the exposed sides of the MTJ device still remains.
All of the aforedescribed processes have the disadvantageous property of allowing the sides of the MTJ device to be exposed and, thereby, to allow shorting between MTJ layers and surrounding current carrying electrodes. The series of figures to be discussed below as FIGS. 6a-h, 7a-b and 8a-b will describe preferred embodiments of the present invention that will eliminate this shorting problem while still retaining the uniform spacing between the free layer and the conducting line formed above the cell element.
A search of the published prior art discloses several other patents and published applications that all teach an improvement of the interaction of MTJ elements and surrounding current carrying lines. Jones et al. (U.S. Pat. No. 6,555,858) teaches a flux concentrating scheme in which magnetic sidewalls are formed on current carrying lines. Kim et al. (U.S. Pat. No. 6,475,857) teaches a scalable device (a device that can be reduced in size while retaining advantageous coupling properties to word and bit lines). Kim et al. (U.S. Pat. No. 6,806,096), Grynkewich et al. (U.S. Pat. No. 6,881,351), Durlam et al. (U.S. Pat. No. 6,174,737), Grynkewich et al. (US Patent Application 2004/0205958) and Shi (US Patent Application 2004/0191928) all teach improved methods of masking dielectric and metal layers during the formation of MTJ elements and associated word and bit lines. None of these prior art references deal directly with the problem of shielding the MTJ element itself so that the planarization processes required to form uniformly flat topographies can work effectively and not lead to conditions that enhance the current leakage from the MTJ element to surrounding current carrying lines.
Accordingly, it is the object of the present invention to devise a novel process for rendering the upper surfaces of MTJ devices and surrounding insulation co-planar, while avoiding the difficulties just discussed in the creation of electrical short circuits as a result of current leakage between the MTJ device and surrounding current carrying lines.